Vulnerabilities (CVE)

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Filtered by vendor Amd Subscribe
Filtered by product Epyc 7313
Total 55 CVE
CVE Vendors Products Updated CVSS v2 CVSS v3
CVE-2020-12966 1 Amd 214 Epyc 7001, Epyc 7001 Firmware, Epyc 7002 and 211 more 2022-10-25 2.1 LOW 5.5 MEDIUM
AMD EPYC™ Processors contain an information disclosure vulnerability in the Secure Encrypted Virtualization with Encrypted State (SEV-ES) and Secure Encrypted Virtualization with Secure Nested Paging (SEV-SNP). A local authenticated attacker could potentially exploit this vulnerability leading to leaking guest data by the malicious hypervisor.
CVE-2021-26322 1 Amd 114 Epyc 7232p, Epyc 7232p Firmware, Epyc 7251 and 111 more 2022-10-25 5.0 MEDIUM 7.5 HIGH
Persistent platform private key may not be protected with a random IV leading to a potential “two time pad attack”.
CVE-2021-26338 1 Amd 88 Epyc 7232p, Epyc 7232p Firmware, Epyc 7252 and 85 more 2022-10-24 7.8 HIGH 7.5 HIGH
Improper access controls in System Management Unit (SMU) may allow for an attacker to override performance control tables located in DRAM resulting in a potential lack of system resources.
CVE-2021-26336 1 Amd 190 Epyc 7002, Epyc 7002 Firmware, Epyc 7003 and 187 more 2022-10-07 4.9 MEDIUM 5.5 MEDIUM
Insufficient bounds checking in System Management Unit (SMU) may cause invalid memory accesses/updates that could result in SMU hang and subsequent failure to service any further requests from other components.
CVE-2020-12944 1 Amd 114 Epyc 7232p, Epyc 7232p Firmware, Epyc 7251 and 111 more 2022-10-06 4.6 MEDIUM 7.8 HIGH
Insufficient validation of BIOS image length by ASP Firmware could lead to arbitrary code execution.
CVE-2021-26337 1 Amd 224 Epyc 7002, Epyc 7002 Firmware, Epyc 7003 and 221 more 2022-09-09 2.1 LOW 5.5 MEDIUM
Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA read from invalid DRAM address to SRAM resulting in SMU not servicing further requests.
CVE-2021-46778 1 Amd 358 Athlon 3050ge, Athlon 3050ge Firmware, Athlon 3150g and 355 more 2022-08-19 N/A 5.6 MEDIUM
Execution unit scheduler contention may lead to a side channel vulnerability found on AMD CPU microarchitectures codenamed “Zen 1”, “Zen 2” and “Zen 3” that use simultaneous multithreading (SMT). By measuring the contention level on scheduler queues an attacker may potentially leak sensitive information.
CVE-2020-12946 1 Amd 88 Epyc 7232p, Epyc 7232p Firmware, Epyc 7252 and 85 more 2022-07-08 6.6 MEDIUM 7.1 HIGH
Insufficient input validation in ASP firmware for discrete TPM commands could allow a potential loss of integrity and denial of service.
CVE-2020-12954 1 Amd 116 Epyc 7001, Epyc 7001 Firmware, Epyc 7002 and 113 more 2022-07-08 2.1 LOW 5.5 MEDIUM
A side effect of an integrated chipset option may be able to be used by an attacker to bypass SPI ROM protections, allowing unauthorized SPI ROM modification.
CVE-2021-26339 1 Amd 168 Epyc 72f3, Epyc 72f3 Firmware, Epyc 7313 and 165 more 2022-05-23 4.9 MEDIUM 5.5 MEDIUM
A bug in AMD CPU’s core logic may allow for an attacker, using specific code from an unprivileged VM, to trigger a CPU core hang resulting in a potential denial of service. AMD believes the specific code includes a specific x86 instruction sequence that would not be generated by compilers.
CVE-2021-26349 1 Amd 46 Epyc 72f3, Epyc 72f3 Firmware, Epyc 7313 and 43 more 2022-05-20 2.1 LOW 5.5 MEDIUM
Failure to assign a new report ID to an imported guest may potentially result in an SEV-SNP guest VM being tricked into trusting a dishonest Migration Agent (MA).
CVE-2021-26342 1 Amd 76 Epyc 7001, Epyc 7001 Firmware, Epyc 7251 and 73 more 2022-05-19 2.1 LOW 3.3 LOW
In SEV guest VMs, the CPU may fail to flush the Translation Lookaside Buffer (TLB) following a particular sequence of operations that includes creation of a new virtual machine control block (VMCB). The failure to flush the TLB may cause the microcode to use stale TLB translations which may allow for disclosure of SEV guest memory contents. Users of SEV-ES/SEV-SNP guest VMs are not impacted by this vulnerability.
CVE-2021-26348 1 Amd 46 Epyc 72f3, Epyc 72f3 Firmware, Epyc 7313 and 43 more 2022-05-19 2.1 LOW 5.5 MEDIUM
Failure to flush the Translation Lookaside Buffer (TLB) of the I/O memory management unit (IOMMU) may lead an IO device to write to memory it should not be able to access, resulting in a potential loss of integrity.
CVE-2021-26370 1 Amd 98 Epyc 7002, Epyc 7002 Firmware, Epyc 7232p and 95 more 2022-05-18 6.6 MEDIUM 7.1 HIGH
Improper validation of destination address in SVC_LOAD_FW_IMAGE_BY_INSTANCE and SVC_LOAD_BINARY_BY_ATTRIB in a malicious UApp or ABL may allow an attacker to overwrite arbitrary bootloader memory with SPI ROM contents resulting in a loss of integrity and availability.
CVE-2021-26324 1 Amd 46 Epyc 72f3, Epyc 72f3 Firmware, Epyc 7313 and 43 more 2022-05-16 7.2 HIGH 7.8 HIGH
A bug with the SEV-ES TMR may lead to a potential loss of memory integrity for SNP-active VMs.
CVE-2021-26332 1 Amd 46 Epyc 72f3, Epyc 72f3 Firmware, Epyc 7313 and 43 more 2022-05-16 6.6 MEDIUM 7.1 HIGH
Failure to verify SEV-ES TMR is not in MMIO space, SEV-ES FW could result in a potential loss of integrity or availability.
CVE-2021-46771 1 Amd 46 Epyc 72f3, Epyc 72f3 Firmware, Epyc 7313 and 43 more 2022-05-16 7.2 HIGH 7.8 HIGH
Insufficient validation of addresses in AMD Secure Processor (ASP) firmware system call may potentially lead to arbitrary code execution by a compromised user application.
CVE-2021-26335 1 Amd 116 Epyc 7001, Epyc 7001 Firmware, Epyc 7002 and 113 more 2022-05-12 7.2 HIGH 7.8 HIGH
Improper input and range checking in the AMD Secure Processor (ASP) boot loader image header may allow an attacker to use attacker-controlled values prior to signature validation potentially resulting in arbitrary code execution.
CVE-2020-12951 1 Amd 116 Epyc 7001, Epyc 7001 Firmware, Epyc 7002 and 113 more 2022-05-12 4.4 MEDIUM 7.0 HIGH
Race condition in ASP firmware could allow less privileged x86 code to perform ASP SMM (System Management Mode) operations.
CVE-2021-26312 1 Amd 114 Epyc 7232p, Epyc 7232p Firmware, Epyc 7251 and 111 more 2022-05-11 2.1 LOW 5.5 MEDIUM
Failure to flush the Translation Lookaside Buffer (TLB) of the I/O memory management unit (IOMMU) may lead an IO device to write to memory it should not be able to access, resulting in a potential loss of integrity.