The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address (MTVEC) register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of service.
References
Link | Resource |
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https://riscv.org/news/2021/08/video-glitching-risc-v-chips-mtvec-corruption-for-hardening-isa-adam-zabrocki-and-alex-matrosov-def-con-29/ | Exploit Vendor Advisory |
Configurations
Information
Published : 2021-08-13 09:15
Updated : 2021-08-23 13:30
NVD link : CVE-2021-1104
Mitre link : CVE-2021-1104
JSON object : View
CWE
CWE-908
Use of Uninitialized Resource
Products Affected
risc-v
- instruction_set_manual